1. Field of the Invention
The present invention relates to a logic circuit of low power dissipation adopted for a large-scale integrated circuit, to a computer system employing the logic circuit, and to a method of designing the logic circuit.
2. Description of the Prior Art
CMOS logic circuits play an important role in integrated circuits because they basically pass no DC current. The power requirement of CMOS logic circuits, although once thought comparatively low, is rapidly becoming a major concern in design of personal information systems and large computer. The power dissipation P.sub.d of a CMOS logic circuit is a dynamic loss, or the power dissipation P.sub.d is mainly caused when charging and discharging load, and is proportional to a square of a high level source voltage V.sub.DD supplied to the circuit as follows: ##EQU1## where C is the effective capacitance per gate. The CMOS logic circuits usually operate between a high level source voltage and a low level source voltage such as a ground (GND) voltage. As is apparent in the expression (1), the power dissipation P.sub.d effectively decreases if the high level source voltage V.sub.DD is scaled down. Lowering of the high level source voltage V.sub.DD, however, has drawbacks such as decreasing the drift velocity of electrons in transistors and decreasing a drain current of the transistors. By such drawbacks, the lowering of the high level source voltage V.sub.DD increases a gate delay time and deteriorates the performance of the logic circuit.
Now, a logic circuit having CMOS gates operating with different supply voltages is reviewed as an example of the art for minimization of the power dissipation. FIG. 1A shows a CMOS logic circuit consisting of first and second CMOS inverters according to a prior art. The first CMOS inverter operates on a lower supply voltage VDDL and the second CMOS inverter on a higher supply voltage VDDH. The first and second inverters are directly connected to each other, and if a node N1 between the first and second inverters is at the lower supply voltage VDDL and if VDDL&lt;VDDH-.vertline.Vthpl.vertline., a p-channel MOS transistor MP1 of the second inverter is not completely turned off to thereby generate a short-circuit current (or DC current) through the second inverter. In this specification, "Vthp" represents the threshold voltage of a pMOS, "Vthn" the threshold voltage of an nMOS, "pMOS" a p-channel MOS transistor, and "nMOS" an n-channel MOS transistor.
Since the pMOS MP1 is incompletely turned off, the short-circuit current flows from a power supply of the higher supply voltage VDDH toward a ground through the second inverter. If the first inverter operates on the higher supply voltage VDDH and the second inverter on the lower supply voltage VDDL contrary to the case of FIG. 1A, no short-circuit current will flow through the second inverter. This is because an input voltage to the second inverter is the higher supply voltage VDDH to completely turn off the pMOS MP1 of the second inverter.
FIG. 1B shows a level converter interposed between gates operating on different supply voltages in a CMOS logic circuit, to prevent the short-circuit current and reduce power dissipation. Although the level converter blocks the short-circuit current, it consumes relatively large dynamic power when it carries out a switching operation. If the CMOS logic circuit must have many level converters, the power dissipation thereof will increase.
FIG. 2A shows a CMOS logic circuit according to the prior art. The expression (1) tells that lowering the high level source voltage V.sub.DD is effective to reduce the power dissipation of a CMOS logic circuit. It is impossible, however, to drop the high level source voltage of every gate in the CMOS circuit because it will make some gates involved in critical paths unable to secure timing requirements. If the timing requirements are not secured, the total operation speed of the circuit will drop. In FIG. 2A, some gates that are not involved in critical paths are selected and set to operate on a lower supply voltage VDDL. To achieve this, the level converter of FIG. 1B must be interposed between a gate operating on the lower supply voltage VDDL and a gate operating on a higher supply voltage VDDH, to prevent a short-circuit current, in practice.
From this point, FIG. 2B shows the modified CMOS logic circuit of FIG. 2A provided with the level converters. In the circuit, some gates operate on the higher supply voltage VDDH and the others on the lower supply voltage VDDL. The number of the level converters used for these gates is large to dissipate large power, and therefore, the circuit of FIG. 2B is undesirable in terms of power dissipation.
Techniques about level converters and arts for reducing power consumption and power dissipation are disclosed in Japanese Unexamined Patent Publication (JUPP) Nos. 4-168805, 4-227318, and 2-198099. The JUPP 4-168805 discloses a dynamic level shifter that passes no short-circuit current. The level shifter carries out a sampling operation according to a clock signal and employs a cross-linked dynamic sense circuit, to reduce power dissipation and secure a high-speed operation. The JUPP 4-227318 discloses a BiCMOS buffer circuit by which an ECL level signal (lower voltage level such as from -0.9 to -1.7 Volts) is converted into a CMOS level signal (higher voltage level signal such as from 0 to 5 Volts) as quickly as possible. The JUPP 2-198099 discloses a vertical ROM (dynamic ROM) incorporating a power source clamp made of a differential amplifier and an FET. A lowered voltage (3V) by the power source clamp is used to precharge a memory array and as a source voltage for a level converter disposed after the memory array. The output of the level converter is transmitted to an external circuit operating with a higher voltage (5V). This technique improves a read speed without increasing a circuit scale or power consumption.
As mentioned above, a CMOS logic circuit may be preferred to have mixed gates operating on a lower supply voltage VDDL and gates operating on a higher supply voltage VDDH. However, any gate operating on VDDH and connected after the gate operating on VDDL generates a short-circuit current. To prevent the short-circuit current, the level converter must be arranged between them. The level converter dissipates relatively large power. If the circuit must have many level converters, the power dissipation thereof will increase to nullify the effort of decreasing power dissipation by using the two supply voltages VDDL and VDDH. As a result, the prior arts hardly reduce the power dissipation of CMOS logic circuits.